Performances And Limitations Of A Technique For Background Calibration Of Capacitor Mismatch Errors In Pipelined A/D Converters
نویسندگان
چکیده
This paper analyses the performances of a recently proposed background calibration technique with digital cancellation of D/A converter noise, which has been recently proposed for highspeed, high-resolution, pipelined Analog-to-Digital Converters (ADCs).
منابع مشابه
Analysis of Integral Nonlinearity in Radix-4 Pipelined Analog-to-Digital Converters
In this paper an analytic approach to estimate the nonlinearity of radix-4 pipelined analog-to-digital converters due to the circuit non-idealities is presented. Output voltage of each stage is modeled as sum of the ideal output voltage and non-ideal output voltage (error voltage), in which non-ideal output voltage is created by capacitor mismatch, comparator offset, input offset, and finite ga...
متن کاملBackground Digital Calibration Techniques for Pipelined ADC’sy
A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC’s) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDAC’s) commonly used in multi-step or pipelined ADC’s. This background calibration process can replace, in effect, a trimming procedure usually done...
متن کاملBackground Digital Calibration Techniques for Pipelined ADCTMs - Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC’s) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDAC’s) commonly used in multistep or pipelined ADC’s. This background calibration process can replace, in effect, a trimming procedure usually done ...
متن کاملBackground digital error correction technique for pipelined analog-digital converters
This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same ...
متن کاملBackground Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy
The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the ...
متن کامل